Intel ahead of schedule with new Xeon server chips

Intel is set to start production of its next-generation Xeon quad-core server chips ahead of schedule, which could then appear in systems as early as the first quarter of next year, a company official said on Tuesday.

“We’re on track for production in the first quarter,” said Kirk Skaugen, vice president and general manager of Intel’s server platforms group during an interview at the Intel Developer Forum. The chips will ship to system makers, and servers based on those chips could appear just “around that same time frame,” Skaugen said.

The chips will be manufactured using the 32-nanometer process and be part of the Xeon 5000 line of processors. The chips will be based on the Westmere microarchitecture, and will carry numerous upgrades over Xeon server chips available today which are made using the 45-nm process.

“It’s ahead of our expectations from a production, qualification and a ramp perspective. That’s good news,” Skaugen said. The chip could go into two- and four-socket servers.

Westmere is a process shrink of the Nehalem microarchitecture, which forms the basis of existing Xeon 5500 server chips. Nehalem brings numerous performance improvements by integrating a memory controller, which provides the CPU a faster access path to memory. The microarchitecture also provides a faster pipe for the CPU to communicate with system components like a graphics card.

Westmere will bring improved performance and power benefits realized from new technology applied to the advanced manufacturing process, Skaugen said. The Westmere chip reduces power leakage by up to 30 times compared to the 45-nm manufacturing process, Intel has said.

Westmere adds a new instruction set for faster encryption and decryption of data called Advanced Encryption Standard (AES), Skaugen said. That could help secure data residing in servers and the cloud, he said. The chip also includes features that could secure data in virtualized environments.

The server chips will be able to run two threads per core, meaning a quad-core chip can run eight threads simultaneously. This feature carries on from existing Nehalem chips.

Intel will start manufacturing 32-nanometer chips in the fourth quarter of 2009, though initial chips are expected to go into laptops and desktops. Intel said production of chips for mainstream systems code-named Arrandale and Clarkdale will start in the fourth quarter this year.

However, Clarkdale chips for desktops could also go into entry-level servers that start at prices under US$500, Skaugen said. Clarkdale will integrate graphics processors alongside the CPU in a two-chip package.

Skaugen also said the company will maintain a two-year chip development cycle for its Itanium line of server chips, which are typically used in enterprise servers requiring high uptime. After multiple delays, Intel is set to release its latest Itanium chip codenamed Tukwila in the first quarter of next year, while its successor, codenamed Poulson, could make an appearance two years later, Skaugen said. The Poulson chip will be manufactured using the 32-nm process.

The company also showed off its first 22-nm wafer on Tuesday at the show. The 22-nm wafer was displayed by Intel CEO Paul Otellini during a morning keynote, which included 364 million bits of SRAM memory and more than 2.9 billion transistors in an area the size of a fingernail.

The 22-nm process will be used to make chips based on the Sandy Bridge microarchitecture, which will be the successor to the Nehalem microarchitecture. Sandy Bridge will feature a new graphics core and new instruction sets that could improve system performance, Otellini said.

The company is expected to shift to the 22-nm manufacturing process in the fourth quarter of 2011, and to the 15-nm manufacturing process in 2013.

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Jim Love, Chief Content Officer, IT World Canada

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Agam Shah
Agam Shah
Agam Shah is a reporter for the IDG News Service in New York. He covers hardware including PCs, servers, tablets, chips, semiconductors, consumer electronics and peripherals.

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