Intel held a candid roadmap discussion on Monday, outlining its product plans for the next five years starting with the renaming of its transistor nodes.
In its new nomenclature, Intel will no longer use nanometre (nm) to denote different node generations. Starting with its enhanced 10nm SuperFin FinFET, Intel will mark node advancement with a number. Its enhanced 10nm node will just be called Intel 7. After that, its 7nm will be renamed to Intel 5 and its refinement, 7nm+, to Intel 3.
After 4, Intel will enter what it calls the angstrom era. The first generation angstrom node will be called Intel A20, followed by A18 in 2025. The move into angstrom will also introduce Intel’s first gate-all-around transistor called RibbonFET.
The node rename is to help shift the perception that Intel’s transistors are “larger” than its competitors. While nanometre once defined the actual size of the transistors in the semiconductor industry, its definition has evolved from a unit of measurement to simply indicate a generational leap, a development that seemed most prominent when the industry introduced 3D FinFETs.
The big rename and expected features
|10nm Enhanced SuperFin
|10 to 15 per cent performance-per-watt gain over current Intel 10nm SuperFin through transistor optimizations, including increased strain, more low-resistance materials, novel high-density patterning techniques, streamlined structures and better routing with a higher metal stack. Arriving in Alder Lake for clients in 2021 and Sapphire Rapids for servers in Q1 2022.
|Intel 7nm FinFET
|20 per cent performance-per-watt over Intel 7. First to use extreme ultraviolet lithography (EUV) developed in partnership with ASML. Ready for production in H2 2022, shipping in products in 2023. First arriving in Meteor Lake for clients and Granite Rapids for servers.
|Intel 7nm+ FinFET
|18 per cent performance-per-watt over intel 4. Denser performance library, increased drive current, optimized interconnect metal stack, and increased use of EUV compared to Intel 4. Begins manufacturing products in H2 2023.
|Angstrom era. Introduces PowerVia and gate-all-around transistor (RibbonFET). Ramp in 2024.
If FinFETs have made the nanometres label nearly irrelevant, it will become even less so when the industry adopts the gate-all-around (GAA) transistor design. TSMC will switch to GAA with its 2nm node in 2023, while Samsung will begin theirs at 3nm in 2022.
There’s a good reason why the industry stuck with the archaic naming scheme: marketing. Typically, shrinking the transistor increases power efficiency and density. Power efficiency is a no-brainer; if the transistor can offer the same or better performance for less energy, it’s easier to build more power-efficient chips. Higher density provides similar benefits. Being able to pack more transistors in the same or smaller area allows for more functions and increases performance. Therefore, smaller transistors have become almost synonymous with cutting edge–and it certainly looks good in marketing materials.
But nanometre has long since lost its meaning, partly because each manufacturer has different methods of measurement, and partly because transistor quality is determined by more than just a single number. Beyond the transistors themselves, the contacts, channel, metal stack and other components all play a part in the overall performance.
To confuse matters further, manufacturers sometimes designate a new number for an optimized version of the same node. For example, TSMC’s 12nm was actually a refined version of its 16nm node.
Thus, it’s a mistake to directly compare transistor sizes between different manufacturers. For example, it’s incorrect to assume that TSMC’s 7nm transistors are 30 per cent smaller than Intel’s 10nm.
Intel is currently preparing its fabs in Oregon, Ireland, Arizona and Israel for these new manufacturing processes.