Servers with new Xeon E5 chips based on the Sandy Bridge microarchitecture will become available early next year, Intel officials said on Tuesday.
The E5 chip will have up to eight processing cores and be able to run 16 threads per socket, said Kirk Skaugen, vice president and general manager of Intel’s Data Center Group, at the Intel Developer Forum in San Francisco. The chip has already started shipping in volume and will deliver significantly higher performance than current Xeon chips, Skaugen said.
“This is the most phenomenal chip we’ve delivered on Intel to the server market,” Skaugen said.
The chip is targeted at high-performance computing and cloud providers, Skaugen said. The Xeon E5 will succeed the Xeon 5600 chips, which were released around the middle of last year and were based on the Westmere architecture.
Intel is targeting the chip at servers with between two and four sockets. Intel already offers low-end Xeon E3 chips based on the Sandy Bridge microarchitecture for servers with up to two sockets. The company also offers Xeon E7 chips, based on the older Westmere architecture, with up to 10 cores for servers with more than four sockets.
Intel has 400 server design wins already for the chip, which is almost double that of the Xeon 5500 chips that were released in 2009, Skaugen said. The chip will compete with new server chips based on the Bulldozer microarchitecture from Advanced Micro Devices. AMD earlier this month said it had started shipping its 16-core Interlagos chips to server makers, who would release products in the fourth quarter.
The chip also boasts some chip enhancements for Intel. This is the first time Intel will integrate the PCI-Express bus in the microprocessor, Skaugen said. That will improve data throughput inside servers while saving power.
Intel did not share further details about the E5 chip such as clock speed, cache or backward socket compatibility. Further details about the chip will come at a later date, an Intel spokesman said.
Skaugen also reiterated the company’s commitment to the Itanium chip, saying it will be able to co-exist with Xeon chips, and the difference between the two was mainly about operating systems.
Xeon and Itanium chips have many common error-correction and RAS (reliability, availability and serviceability) features demanded by high-end servers, but are based on different architectures. Itanium is designed for mainframe operating systems and Unix flavors such as Hewlett-Packard’s HP-UX, while Xeon chips could work with Windows, Linux and Sun’s SPARC environments, Skaugen said.
“There’s no workload in the world that cannot run on Xeon processors,” Skaugen said.
While Skaugen plugged Xeon, he also said that the next Itanium chip, code-named Poulson, would deliver double the performance of current Itanium chips and be in production next year.
IDF will run through Thursday in San Francisco’s Moscone Convention Center.
