Knowing that there’s a limit to how many cores can be put on a chip, processor designers are looking to a tiled architecture as the next generation of chip design.
The agenda of the 19th annual Hot Chips conference going on this week at Stanford University in Palo Alto, California, includes presentations from different chip companies on parallel computing using a tiled, or grid design. The conference, which has drawn an estimated 600 academics, technology researchers and chip company engineers, ends Tuesday.
Tiles, each with a processor core and a router, are laid end to end and in rows, looking like a grid map of a city. Instructions jump from tile to tile along their route back and forth across the chip. Different instructions can run parallel to each other simultaneously without having to wait for one another. Parallel computing uses less energy than do today’s multicore chips.
Intel Corp. detailed a prototype 80-core processor made up of tiles laid out eight across and 10 down. Intel’s chip also has a “sleep/wake” function that turns off power to some tiles when they are idle and wakes them up when they are needed, said Yatin Hoskote, principal engineer at Intel. Parallelism makes it possible to run a communication instruction concurrently with a computational instruction, he said.
